1.25/2.5-Gb/s Dual Bit-Rate Burst-Mode Clock Recovery Circuit Using Gated-Oscillators
نویسندگان
چکیده
A burst-mode clock recovery circuit with a novel dual-mode structure is presented. It utilizes two gated-oscillators to align recovered clock edges to data. It can operate in double data-rate mode in which both rising and falling edges of recovered clock are used. To enable this, gated-oscillator reset-phase control scheme is introduced to switch the starting phase of gated-oscillator dynamically between 0° and 180° according to current clock phase. A prototype chip was designed with 0.18μm CMOS technology, whose 1.25/2.5-Gb/s dual-mode clock recovery operation is successfully verified by SPICE simulation.
منابع مشابه
1.25/2.5-Gb/s Dual Bit-Rate Burst-Mode Clock Recovery Circuits in 0.18- μħbox m CMOS Technology
—A burst-mode clock recovery circuit with a novel dual bit-rate structure is presented. It utilizes two gated-oscillators to align clock with data edges and can operate in half-rate clocking mode, doubling data throughput, as well as in full-rate clocking mode. The gated-oscillator reset-phase control scheme causes the starting phase of gated-oscillators to alternate repeatedly between 0° and 1...
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